JK flip flops are counters obtained by connecting them repeatedly. The clock signal is applied only to the first flip-flop. The second flip-flop is connected to the output of the first flip flop. The third flip-flop is connected to the output of the second flip-flop. Outputs are obtained from Q outputs.Asynchronous counters also experience a time delay between input and output because the clock signal is applied only to the first flip flop.An Asynchronous counter can have a possible counting stateof 2 n-1; Mod-16 (0-15) for a 4-bit counter is ideal for use in Applications with Frequency Division. However, it is also possible to use the basic asynchronous counter configuration to create custom counters with counting states less than the maximum number of outputs. It is obtained by forcing the counter itself to zero at a predetermined value by producing a type of asynchronous counter with truss arrays. Then, an n-bit counter that counts to the maximum module (2n)is called a full array counter, and an n-bit counter whose module is less than the maximum possible is called a dashed counter. But why would we want to create an asynchronous truncated counter that doesn't have mod-4, MOD-8, or any other module equal to the power of two? The answer is that we can do it using union logic to take advantage of the asynchronous inputs in the flip-flop. If we take the MOD-16 asynchronous counter and replace it with additional logic gates, we will have made the decimal counter for use in standard decimal counting and arithmetic circuits. Such counters are often called decade counters. A decimal counter requires that when the number of outputs reaches a decimal value of 10, that is, it reaches zero. When it is DCBA = 1010, and to do this we need to feed this condition back to the reset entry. If the binary is a counter with a counting sequence between "0000" (BCD = "0") and "1001" (BCD = "9"), the BCD (binary decimal) counter is called.
Such asynchronous counters count upwards on each back edge of the clock signal until an output reaches 1001 (decimal 9) starting at 0000. Both QA and QD outputs are now equal to logical "1". In the implementation of the next clock pulse, the output from the 74LS10 NAND pass changes the state from "1" to the logical "0". Because the output of the NAND pass depends on the CLEAR (CLR) inputs of all 74LS73 JK Flip-flops, this signal causes all Q outputs to be reset to binary 0000 out of 10. Because QA and Flip-flops as QA and Outputs have just been reset, both QD are now equal to logical "0", the output of the NAND pass returns to the "1" logic level, and the counter restarts from 0000. That's how we can create our tenth counter circuit.
Decimal Counter Accuracy Table
|Time Counter||Output Status||Decimal Value (Decimal)|
|11||Resets Counter Outputs|
Decimal Counter Schedule Chart
Using the same idea as interrupting counter output arrays, the above circuit can be easily adapted to other counting cycles simply by changing connections to the inputs of the NAND gateway or using other logic gateway combinations. For example, a twelve-scale (modulo-12) can be easily made by taking inputs to the NAND pass from outputs in "QC" and "QD", where the binary equivalent of 12 is 1100. this output "QA" is the least meaningful bit (LSB). Since the maximum module that can be applied with a flip-flop is2 n, this means that when designing cut asynchronous counters, you need to determine the lowest power of two that are larger or equal to the module you want. Let's say we count from 0 to 39 or mod-40 and repeat. Then the maximum number of flip-flops required is six, n = 6 gives the maximum MOD 64, because five flip-flops will not be enough because this only gives us MOD-32. Now, suppose we want to create a "divide by 128" counter for the frequency section, in this case, it becomes n=7 and we get our target number 128 128 = 27. We're going to have to cascade seven flip-flops. An easy alternative is to use two TTL 7493s as a 4-bit surge counter/divider. Because 128 = 16 x 8, one 7493 can be configured as a "divide by 16" counter and the other as an "divide by 8" counter. The two integrated, as shown in "dividing by 128" will be cascaded together to create a frequency divider. Of course, standard integrated asynchronous counters such as the TTL 74LS90 programmable surge counter/divider are available, which can be configured as a 2-by-2 split, 5-by-5 split, or any combination of both. The 74LS390 is a very flexible dual-ten drive integrated with numerous "partition" combinations ranging from 2, 4, 5, 10, 20, 25, 50 and 100.
The ability of the surge counter to cut arrays to produce a "divide by n" output means that counters, and especially surge counters, can be used as frequency dividers to reduce the high clock frequency to a more useful value for digital use. For example, suppose we need an accurate 1Hz timing signal to run a digital clock. Using a standard 555 timer integrated configured as an unstable Multivibrator, we can produce the 1 Hz frame wave signal quite easily, but we must take into account that the manufacturer datasheet tells us that the 555 timer has a typical 1-2% timing error depending on the manufacturer. However, the datasheet also tells us that the maximum operating frequency of the 555 timer is about 300 kHz, and it would be acceptable for a 2% error at this high frequency, but still about 6 kHz to be large at the maximum. Therefore, by choosing, for example, a higher timing frequency of 262.144kHz and a surge of 18 bits (MOD-18) counter, we can easily make a precise timing signal of 1 Hz, as shown below.
This, of course, is a very simple example of how to produce accurate timing frequencies, but using high frequency crystal oscillators and multi-bit frequency dividers, precise frequency generators can be produced for a wide range of applications, from clocks or clocks to event timing. and even electronic piano/synthesizer or music genre applications. Unfortunately, one of the main drawbacks of asynchronous meters is that there is a small delay between the arrival of the clock pulse at the entrance and its availability at its exit due to the internal circuit of the door. In asynchronous circuits, this delay is called Propagation Delay, which gives the asynchronous surge counter the nickname "propagation counter", and in some high frequency cases this delay can produce incorrect output numbers. In large bit surge counter circuits, if the delay of separate stages is collected to ensure a total delay at the end of the counter chain, the time difference between the input signal and the counted output signal can be very large. Therefore, the Asynchronous Counter is usually not used in high frequency counting circuits, including a large number of bits. Also, outputs from the counter do not have a fixed time relationship with each other and do not occur at the same time due to time sequences. In other words, output frequencies become available one by one, a kind of domino effect. Then, the more flip-flops are added to an asynchronous counter-chain, the lower the maximum operating frequency to ensure accurate counting. Synchronous Counters have been developed to overcome the propagation delay issue.
Then to summarize some advantages of Asynchronous Counters:
- Asynchronous Counters can be easily made from Toggle or D-type flip flops.
- Flip-flops are called "Asynchronous Counters" because not all clock input is driven by the same time signal.
- Each output in the chain depends on a state change from the previous flip flops output.
- Asynchronous counters are sometimes called surge counters, because the data looks like "fluctuating" from the output of one flip-flop to the input of another.
- They can be applied using "divide-n" counter circuits.
- Truncated counters can produce any module count.
Disadvantages of Asynchronous Counters:
- An extra "resynchronize" output flip-flop may be required.
- Extra feedback logic is required to count a cut array that is not equal to 2n.
- When a large number of bits are counted, the propagation delay with consecutive stages can be unintendedly large.
- This delay gives them the nickname "Propagation Counters".
- Counting errors occur at high clock frequencies.
- Synchronous Counters are faster and more reliable because they use the same time signal for all flip-flops.
- In the next tutorial about counters, we will look at the Synchronous Counter and see that the main feature of a synchronous counter is that the clock input of each flip-flop in the chain depends on all flip-flops. clocked simultaneously.