Decoder means translating or decoding encoded information from one format to another. Thus, the binary decoder converts the binary input signals "n" to an equivalent code using 2n outputs.
If binary decoder receives n entries (typically grouped as a single binary or Boolean number), it enables one and only one of the 2^n outputs based on this entry when all other outputs are disabled.
For example, an inverter (Logic NOTE Gate) can be classified as a 1×2 binary decoder, because 1-input and 2-output (21) are possible, then we can say that a standard combinational logic decoder is a nxm decoder, where m ≤ 2n and output Q depend only on current input states. In other words, a binary decoder looks at its existing entries, determines which binary code or binary number is included in their input, and selects the appropriate output corresponding to that binary entry.
A binary decoder converts encoded entries into encoded outputs; Here the input and exit codes are different. Decoders can typically be used to "decode" a binary or BCD (code 8421) input pattern into a decimal code. Commonly found BCD-decimal decoders include TTL 7442 or CMOS 4028. In general, the exit code of decoders usually contains more bits than the input code, and practical "binary decoder" circuits include line configurations from 2 to 4, 3 to 8, and 4 to 16.
2×4 Binary Decoders
This simple example above of a binary decoder from 2 to 4 consists of four VE gates. The binary input labeled A and B is resolved to one of 4 outputs, so the description of 2 to 4 binary decoders. Each output will represent one of the minitherms of the 2 Input variables. (each output = one miniterm)
Binary inputs A and B determine which output line from Q0 to Q3 is "high" at the logic level "1", while the remaining outputs are kept "low" in the logic "0". Thus, only one outlet can be active (high) at any time. Therefore, whichever output line is "high" identifies the binary code in the entry.
Some binary decoders have an additional input pin labeled "Enable", which controls outputs from the device. This extra input ensures that the outputs of decoders are "on" or "off" as needed. Such binary decoders are commonly used as "memory Address decoders" in microprocessor memory applications.
We can say that the binary decoder is a demultiplexer with an additional data line used to activate the decoder. An alternative way to look at the decoder circuit is to see inputs a, b and C as address signals. Each combination of A, B, or C defines a unique memory address.
We found that a 2-4-line binary decoder (TTL 74155) can be used to provide four outputs, one for each possible input combination, and to decode any 2-bit binary code. However, sometimes it is necessary to have a binary decoder with more output than is available, so by adding more input, the decoder can potentially provide 2^n more outputs. For example, a 3-binary entries (n = 3) will work as a decoder, a 3×8-line decoder (TTL 74138), and a 4×16-line decoder (TTL 74154) with 4 inputs (n = 4).
4×16 Binary Decoder Configuration
Entries A, B, C are used to select which output in both decoders will be in the "1" (High) logic. Input D is used with enable input to select which encoder's first or second output will be "1".
However, there is a limit to the number of entries that can be used for a particular decoder, because as n increases, so does the number of doors needed to produce an output. This causes the fan output of the doors used to drive them to be large.
Such active "high"decoder can be applied only using inverters and doors. It is convenient to use an AND door as the basic decoding element for output, because only all inputs produce "high" or logic "1" output when the logic is "1".
However, some binary decoders are built using AND NOT gates for their decoded output. Because AND NOT doors are cheaper because they need fewer transistors to apply in their designs.
2X4 NAND Binary Decoder
For NAND decoder, only one output can be low. It can be equal to the logic "0" at any time, and all other outputs will be in high condition. Decoders are also available with an additional "Enable" input pin, which allows the decoded output to be "on" or "off" by applying the logic "1" or "0", respectively. For example, when the enable entry is at the logic level " 0 " (EN = 0), all outputs will be "turned off" in the logic "0", regardless of the status of entries A and B.
Memory Address Decoder
Binary decoders are used in more complex digital systems to access a specific memory location based on an "address" generated by an computing device. In modern microprocessor systems, the amount of memory required can be quite high. One way to overcome this problem is to connect a large number of separate memory chips and read the data on a common "Bus". To prevent data from being "read" from each memory chip at the same time, each memory chip is selected one by one, known as Address decoding.
In this type of application, The Address represents encoded data entry. Outputs are signals for selecting specific memory elements. Each memory chip has an input called Chip Select or CS, which is used by MPU (microprocessor unit) to select the appropriate memory chip when needed. Usually the logic in the chip select (CS) input selects the state "1" state memory device, while a logic "0" state in the input selects it.
Therefore, by selecting or disabling each chip one by one, it allows us to select the correct memory address device for a specific address location. The advantage of address decoding is that when we specify a specific memory address, the corresponding memory location is located only on one of the chips.
For example, suppose we have a very simple microprocessor system with only 1KB (thousand bytes) of RAM memory and 10 lines of memory Address. Memory consists of 128×8-bit (128×8 = 1024 bytes) devices, and we will need 8 separate memory chips for 1Kb, but we will also need a 3×8-line decoder to select the right memory chip.