Frequency Divider / Frequency Division

frequency divider Frequency Divider uses flip-flops with 2-split transition as binary counters to reduce the frequency of the input clock signal In the series of Sequential Logic Circuits, we have seen how the D-type Flip-Flop works and how they can connect to each other to create a D Latch (data latch). Another useful feature of the D-type Flip-Flop is that it has a binary divider or "split by 2" counter for the Frequency Pane. Here the inverted Q output terminal (NOT-Q) connects directly to the data entry terminal D, giving "feedback" to the device, as shown below.

Split Counter by Two
Split Counter by Two

From the above frequency waveforms, through "feedback" from Q to input terminal D, output pulses in Q can be seen to have a frequency of exactly half of the input clock frequency (ε ÷ 2). In other words, frequency division occurs because the circuit now divides the input frequency into two factors (octaves). This then creates a type of counter called ripple counter, and the clock pulse in the ripple counters triggers the first flip-flop, which in turn triggers the third flip-flop, which triggers the second flip-flop to exit, and so on.

Transition flip-flop (T-type / Toggle)

Another circuit element that can be used to divide the frequency is the T-type or Toggle flip-flop. With a small change in a standard JK flip-flop, we can create a new type of flip-flop called Toggle flip-flop. T-type flip-flops can be made from type D flip-flops or standard JK flip-flops such as 74LS73, as shown above. In short, it is a device with only two inputs, one of which is the "Transition/Toggle" entry itself, and as shown, the negative control "Clock/Clock" input.

frequency divider
74LS73 Toggle Flip Flop

A "Transitive flip-flop" takes its name from the flip-flop's ability to switch between two different states, "transition state/toggle state" and "memory state". Since there are only two cases, a T-type flip-flop is ideal for use in frequency splitting and binary counter design. Binary surge counters can be created using "Toggle" or "T-type flip-flops" by connecting one's output to the other's clock input. Transition flip-flops are ideal for creating surge counters as they switch from one state to another (HIGH – LOW or LOW – HIGH) every hour cycle, so simple frequency divider and surge counter circuits can be easily created using the standard T-type. If we serially connect the two T-type flip-flops, the first input frequency is "split in half" by the first flip-flop ( ε ÷ 2 ), and then "split in half" again. The second flip-flop ( ε ÷ 2 ) ÷ 2 effectively gives an output frequency divided four times, after which the output frequency is a quarter (25%) of the original clock frequency (ε ÷ 4). Each time we add another transition or "T-type" flip-flop to the chain, the output clock frequency is halved or divided by 2 again, which continues and gives an output frequency of 2n; where the number "n" is the number of flip-flops used. Toggle or T-type flip-flop is a 2-way split device based on the standard JK-type flip flop with an edge trigger triggered by the rising edge of the watch signal. In short, it is that each bit moves to the right with one or two stops. All flip-flops can be reset asynchronously and triggered to open the front or back edge of the input time signal, making it ideal for the Frequency Section. This type of counter circuit used for the frequency section is commonly known as the Asynchronous 3-bit Binary Counter, since the output from 3-bit wide QA to QC is a binary count from 0 to 7 for each hour pulse. In an asynchronous counter, it is applied only to the first stage with the output of a flip-flop stage that provides a clock signal for the next flip-flop stage, and the next stages are converted from the previous stage at each stage by halving the clock pulse. This arrangement is commonly known as Asynchronous, since not all bits in the counter change at the same time, since each hour event occurs independently. Because the counter counts sequentially from 0 to 7, this type of counter is also known as the "up/up" or "forward/forward" counter (CTU) or "3-bit Asynchronous Up Counter". The three-bit asynchronous counter shown is typical and uses flip-flop in transition mode. Asynchronous "down" numberers (CTDs) are also available.

Accuracy Table for 3-bit Asynchronous Up Counter

Time CycleOutput Bit Model
QCQBQA
0000
1001
2010
3011
4100
5101
6110
7111

Based on this table, we can see that the output from the D-type flip-flop is half the frequency of the input, that is, it counts at 2. By cascading more D-type or Toggle Flip-Flop together, we can make a binary counter circuit in the form of the force of 2 to any value, in fact, 2 times the input clock frequency 2, 4 or 8 times.

Binary Numberers

Thus, we can see that a numberer is nothing more than a custom record or model builder that produces a specific output pattern or sequence of binary values (or states) upon the application of an input pulse signal called "clock". The concept of clocks is actually used for data transfer in these applications. Typically, counters are logic circuits that can increase or decrease a count one by one, but when used as asynchronous counters, they can divide these input pulses by generating a clock-split signal. Counters are created by connecting flip-flops, and any number of flip-flops can be connected to each other or a "cascading" "split-n" binary counter can be created; where "n" is the number of counter stages used and is called module. The module of a counter, or simply the "MOD", is the number of output states that the counter passes before returning itself to zero, that is, a full loop.

Reminder

Getting mode is a mathematical process such as aggregation, subtraction, and so on. In this process, a number is divided into a number and the remaining number is retrieved, and the remaining number is called MOD. For example, if the number 5 is divided by 4, its mode is 1 because the remaining 1. Likewise, when the number 10 is divided by 5, its mode is 0 because the remaining is 0(zero).

In 3-stage counters such as the circuit above, it will count from 0 to 7, that is, 2n-1. It has eight different output states representing decimal numbers from 0 to 7 and is called the Modulo-8 or MOD-8 counter. In 4-step counters, it is counted from 0 to 15 and is therefore called the MOD-16 counter. Eg:

  • 3-bit Binary Counter = 24 = 8 (modulo-8 or MOD-8)
  • 4-bit Binary Counter = 24 = 16 (modulo-16 or MOD-16)
  • 8-bit Binary Counter = 28 = 256 (modulo-256 or MOD-256)

4-bit Modulo-16 Counter

frequency divider Multi-bit asynchronous counters that connect in this way are also called "Surge Counters" or surge dividers, since the state change at each stage appears to "fluctuate" through the counter from the LSB output to the MSB output connection. Surge counters are available in standard IC format from the 74LS393 Dual 4-bit counter to the 74HC4060, a 14-bit surge counter with its own built-in clock oscillator, producing the perfect frequency portion of the base frequency.

Summarize

For the frequency section, flip-flops with transition mode are used as dividing into two counters in a chain. A flip-flop clock divides εINby 2 and two flip-flop εINby 4. One benefit of using a transition flip-flop for the frequency section is that at any point the output has a full 50% duty cycle. The final output time signal will have a frequency value equal to the input clock frequency divided by the MOD number of the counter. Such circuits are known as "division-n" delis. Counters can be created by connecting individual flip-flops and are classified according to the way they are clocked. In asynchronous counters, the (surge counter) is clocked with the first flip-flop external clock pulse, and then each consecutive flip-flop is clocked by the output of the previous flip-flop. In synchronous counters, the clock input connects to all flip-flops so that they are clocked (synchronized) at the same time. In the next tutorial we will look at the Asynchronous counters and see that the main feature of an asynchronous counter is that both stops in the chain deride their own clock from the previous two stops, and therefore independent of the clock of entry.