|Sıralı Mantık Devreleri|
|Sıralı Mantık Devreleri||Shift Register||T-tipi Flip Flop|
|JK Flip Flop||Johnson Ring Sayıcı||D-tipi Flip Flop|
The basic SR NAND Flip Flop circuit has many advantages and usages in sequential logic circuits. However, they may experience great difficulties due to two basic switching problems:
- Set = 0 and Reset = 0 should always be avoided
- If you try to reset the circuit with the Enable (EN) input in high state, the correct locking action may not occur.
This is where JK Flip Flopsare developed to help us. JK Flip Flop is the most widely used of all Flip Flop designs. It is considered a universal Flip Flop circuit all over the world.
Basic JK Flip Flop Circuit
As you can see, the naming of entries has been changed. This nomenclature you've seen is a tribute to Jack Kilby, the developer of JK Flip Flop.
With this type of cross-linking of SR Flip Flop, the situation we have previously avoided, s = "1" and r = "1" status has now become available.
JK Flip Flop Accuracy Table
If both J and K inputs are in a logic "1" state, the circuit outputs will be reversed every time the clock input is high. In other words, they will be changed to complement each other. In short, when both Terminals of the JK Flip Flop are "HIGH", it causes it to behave like a T-type Flip Flop. Since the outputs are fed back into the inputs, it can cause the output in Q to be continuously released between SET and RESET once completed.
Now that we know about JK Flip Flops, we can slowly review an exemplary integration. One of the most used JK Flip Flops today:
- Binary JK Flip Flop 74LS73
Will. In fact, just being familiar with that name will give us some difficulty. So let's look at the internal structure of this integration.
To learn more about this topic, we recommend that you review our Asynchronous Counter circuit consisting of JK Flip Flops.