Junction Area Effective Transistor (JFET)

In the effective transistor tutorials in the bipolar junction area, we found that the transistor's output collector current was proportional to the input current flowing into the base terminal of the device. Thus, since a smaller current can be used to change a larger load current, it makes the bipolar transistor a device (Beta model) that works with "PAST".

However, an area effective transistor or just a FET uses the voltage applied to the input terminal. This is called a gate to control the current flowing through it. This causes the output current to be proportional to the input voltage. Since its operations are based on an electric field (hence the field effect name) generated by the input gate voltage, this then makes the field effect Transistor a device that works with "voltage".

Crossroads Area Effective Transistor
Typical Field Effective
transistor

The field-effect transistor is a three-terminal unipolar semiconductor device with very similar characteristics to its Bipolar transistor counterparts. For example, high efficiency, instant operation, robust and inexpensive, and can be used to replace their cousins of equivalent bipolar connection transistors (bjt) in most electronic circuit applications.

Field-effect transistors can be made much smaller than an equivalent bjt transistor. Combined with low power consumption and power distribution, CMOS is ideal for use in integrated circuits such as digital logic chips.

We remember from previous tutorials that there are two basic bipolar transistor structures, NPN and PNP, that basically describe the physical arrangement of p-type and N-type semiconductor materials in which they are made. This also applies to FET, since there are also two mainly effective transistor Classifications called n-channel FET and P-channel FET.

The field is a three-terminal device built without PN-junctions within the mainstream transport route between the effective transistor, drain and source terminals. These terminals correspond to the collector and emitter of the Bipolar transistor, respectively. The current path between these two Terminals is called a "channel", which can be made of a P-type or an N-type semiconductor material.

Control of the current flowing in this channel is achieved by changing the voltage applied to the gate. As the name suggests, Bipolar Transistors are "Bipolar" devices because they work with both types of charging carriers, holes and electrons. On the other hand, the field-effective transistor is a "unipolar" device that depends only on the transmission of electrons (N-channel) or holes (P-channel).

The field-effective transistor has a significant advantage over its standard bipolar transistor cousins because the input impedance (rn) is very high (thousands of Ohms) and in BJT it is relatively low. This very high input impedance makes them very sensitive to input voltage signals, but the take of this high sensitivity from us will be that they can be easily damaged by static electricity.

There are two main types of metal oxide semiconductor field-acting transistors, or MOSFET for short. The connection area is effective transistor JFET and insulated door area effective transistors (IGFET).

Crossroads Area Effective Transistor

We have previously seen a bipolar connection transistor constructed using two PN-junctions on the mainstream transport road between emitter and collector terminals. Junction Area Effective Transistor (JUGFET or JFET) does not have PN-connections. Instead, the majority has a narrow piece of high-resistant semiconductor material that forms a "Channel" of N-type or P-type silicon to flow through the carriers. Ohmic electrical connections at both ends are called drain and source, respectively.

Junction area effective transistors have two basic configurations: N-channel JFET and P-channel JFET. The channel of the N-channel JFET is contributed by donor impurities. This means that the current flow along the channel is negative (hence the term n-channel) in the form of electrons. Similarly, the channel of the P-channel JFET is contributed by receiving impurities. This means that the current flow along the channel is positive (hence the term p-channel) in the form of holes. N-channel CTTs have a greater channel conductivity (lower resistance) than equivalent P-channel types. Because electrons have a higher mobility along a conductor than holes. This makes the N-channel JFET a more efficient conductor than its P-channel counterparts.

We've previously said that there are two ohmik Electric connections at both ends of the canal called drain and source. However, within this channel there is a third electrical connection called gate terminal. This can also be a P-type or N-type material that forms a pn-junction with the main channel.

The relationship between the connections of the intersection area effective transistor and a bipolar junction transistor is compared below.

Comparison of Connections Between JFET and BJT

Crossroads Area Effective Transistor
Comparison of Connections Between JFET and BJT

The symbols and basic structure for both configurations of Jfets are shown below.

Crossroads Area Effective Transistor

The semiconductor "channel" of the junction area effective transistor is a resistant path in which a voltage VDS causes a current id to flow, and therefore the junction area effective transistor can transmit the current equally well in both directions. Since the channel is resistant in nature, a voltage gradient is formed along the length of the channel, which becomes less positive when going from the drain terminal to the source terminal.

As a result, the pn-junction therefore has a high reverse bias in the drain terminal and a lower reverse bias in the source terminal. This bias leads to the formation of a "depletion layer" within the channel and its width is increased by prejudice.

The size of the current flowing through the channel between the drain and source terminals is controlled by a voltage applied to the gate terminal, which is inversely biased. In an N-channel JFET, this gate voltage is negative, the gate voltage for a P-channel JFET is positive.

The main difference between the JFET and a bjt device is that the gate current is practically zero when the JFET junction is inverted bias, whereas Bjt's base current is always greater than zero.

Bias of an N-Channel JFET

Crossroads Area Effective Transistor

The section diagram above shows an N-type semiconductor channel with a p-type region called gate scattered throughout the N-type channel that forms an inverted biased PN-junction. This is the junction that forms the depletion zone around the gate area when external voltage is not applied. Therefore, jfets are known as exhaustion mode devices.

This depletion zone produces a potential Gradient of varying thickness around the PN-junction. Limits the flow of current along the channel by reducing its effective width and thereby increasing the overall resistance of the channel itself. Then we can see that the most depleted part of the depletion zone is between the gate and the drain, while the least depleted area is between the gate and the source.

Without the external gate voltage (vg = 0) and a small voltage (VDS) applied between drain and source, the maximum saturation current (IDSS) will flow from drain to source through the channel. It will only be limited to the small depletion zone around the intersections.

If a small negative voltage (-VGS) is applied to the Gate, the size of the depletion zone begins to increase. Reduces the overall effective area of the channel and thus reduces the flow through it. Some kind of "squeezing" effect occurs. Therefore, when the reverse biased voltage is applied, the width of the exhaustion zone increases, which reduces the transmission of the channel.

Since the PN-junction is inverted, very little current will flow into the gate connection. When the gate voltage (-VGS) is made more negative, the width of the channel decreases until more current does not flow between drain and source, and FET is said to be "jammed" (similar to the cutting zone for a bjt).

Compressed JFET Channel

Crossroads Area Effective Transistor

Gate voltage controls VGS channel current in this jam zone, and VDS has little or no effect.

As a result, the fet acts as a voltage-controlled resistance with zero resistance when VGS = 0 and maximum "on" resistance (RDS) when the gate voltage is too negative. Under normal working conditions, the JFET gate is always negative biased according to the source. Source is given the output features of an N-channel JFET with a short-circuiting gate as follows:

Exit Characteristic V-I Curves of a Typical FET Junction

Crossroads Area Effective Transistor
Exit Characteristic V-I Curves of a Typical FET Junction

The voltage applied to the Gate controls the current flowing between the VGS, drain and source terminals. VGS refers to the voltage applied between gate and source, while VDS refers to the voltage applied between drain and source.

Since an intersection area is an effective transistor, voltage-controlled device, "no current flows into the gate". The source current (IS) that flows from the device then equals the drain current that flows into it, and therefore ( ID = IS ).

The example of properties curves shown above shows four different working regions for a JFET, which are given as follows:

  • When the ohmic zone-VGS = 0 is, the depletion layer of the channel is very small and acts as a JFET voltage-controlled resistance.
  • Cutting Zone – also known as the jamming zone of the gate voltage, VGS is sufficient to cause JFET to act as an open circuit, as the channel resistance is at its maximum.
  • Saturation or active zone – JFET becomes a good conductor and while the gate source voltage (Vgs) is controlled, the drain source voltage (VDS) has little or no effect.
  • The voltage (VDS) between fault zone-drain and source is high enough to cause the jfet's resistant channel to deteriorate and pass through the uncontrolled maximum current.

The characteristic curves for the effective transistor that takes a p-channel junction are the same as the above, except that the drain current id decreases with VGS, an increased positive gate source voltage. When Vgs = VP, the discharge current is zero. For normal operation, VGS is biased to be somewhere between VP and 0. We can then calculate the drain current, saturation or the identity of any bias point in the active zone as follows:

Drain Current in The Active Zone

Crossroads Area Effective Transistor
Drain Current in The Active Zone

Note that the value of the discharge current is zero and will be between IDSS (maximum current). Knowing the drainage current identity and drainage source voltage VDS, the resistance of the channel (RDS) is given as follows:

Drain Source Channel Resistance

Crossroads Area Effective Transistor
Drain Source Channel Resistance

Where it is: GM is a "transconductance gain" because it is a JFET voltage controlled device and represents the rate of change of drainage current according to the change in door weld voltage.

Modes of Fets

Like the bipolar connection transistor, the field-effect transistor, a three-terminal device, has three different modes of operation and therefore can be connected in a circuit in one of the following configurations.

Public Source (CS) Configuration

Crossroads Area Effective Transistor
Public Source (CS) configuration

In the common resource configuration (similar to a common emitter), the input gate is applied and the output is retrieved from the drain as shown. This is the most common operating mode of FET due to its high input impedance and good voltage amplification, and therefore common welding amplifiers are widely used.

The common welding mode of the FET connection is usually used in Audio frequency amplifiers and high input impedance pre-amplifiers and stages. The output signal, which is an amplification circuit, is 180 degrees" out of phase with input.

Public Gate (CG) Configuration

Crossroads Area Effective Transistor
Public Gate (CG) Configuration

In the common gate configuration (similar to the common base), the input is applied to the source, and the output is taken from the drain with the door connected directly to the soil (0v), as shown. The high input impedance feature of the previous connection is lost in this configuration because the common gate has a low input impedance but a high output impedance.

This type of fefet configuration can be used in high frequency circuits or impedance matching circuits where low input impedance must be paired with high output impedance. The output is "in-phase" with input.

Common Drain (CD) Configuration

Crossroads Area Effective Transistor
Common Drain (CD) Configuration

In the common drain configuration (similar to a common collector), the entrance is applied to the door and the output is taken from the source. The common drain or "source tracker" configuration has high input impedance and low output impedance and close union voltage gain, so it is used in buffer amplifiers. The voltage gain of the weld tracker configuration is less than the union, and the output signal is "in-phase" with the input signal, 0o.

This type of configuration is called "common drain" because there is no signal in the drain connection. The current voltage, +VDD, provides only one bias. The output is in the phase with the input.