MOD Sayıcı / MOD Counter

MOD Counters are gradual counter circuits that count to a specific module value before resetting.

The job of a number is to count the contents of the counter by advancing a number with each hour pulse. Counters that advance number or status sequences when enabled with a clock entry are said to run in a "count" mode. Similarly, counters that reduce number sequences or states when enabled by a clock entry are said to run in "countdown" mode. Counters running in UP and DOWN modes are called bidirectional counters.

Counters are sequential logic devices that are enabled or triggered by an external timing pulse or time signal. A counter can be created to work as a synchronous circuit or asynchronous circuit. In synchronous counters, all data bits change synchronously by applying a clock signal. An asynchronous counter circuit is independent of the clock-in time, so data bits change state at different times one after the other.

Counters are sequential logic devices that then monitor a predetermined sequence of counting states triggered by an external clock (CLK) signal. The number of states or count sequences in which a particular counter progresses before returning to its original initial state is called module (MOD). In other words, the module (or modulo only) is the number of states that the counter counts and the number of dividers of the counter.

Module Counters, or simply MOD counters, are defined by the number of states that the counter will sort before returning to its original value. For example, a2-bitcounter that counts from 00 2 to11 2in binary system, that is, counts from 0 to 3 in decimal, has a module value of 4 (00 → → returns to 10 → 10 → 11 and 00), so it is called modulo-4 or mod-4 counter. Also note that it takes four hours to reach 00 to 11.

As in this simple example, there are only two bits, ( n = 2 ) then the maximum number of possible output state for the counter (maximum module):2 n = 2is 2 or 4. However, counters can be designed to count to any number. To produce a single module or MOD-N counter, a 2n state can be generated in rows by cascading multiple counting stages.

Therefore, a "Mod-N" counter requires a number of flip-flops(n is the number of bits) that are interconnected to count a single data bit while providing 2 n different output states. Note that N is always an integer value.

We can see that MOD counters have a module value of 2, i.e. 2, 4, 8, 16 and so on to produce an n-bit counter depending on the number of flip-flops used, and determine how they are connected, the type and module of the counter.

Type D Flip-Flops

MOD numbers are made using a "flip-flop" and a single flip-flop produces 0 or 1 numbers, giving a maximum number of 2. There are different types of flip-flop designs that we can use, SR, JK. To create a counter of JK Master-slave, type D or even T type flip-flop. However, to keep things simple, we will use the D-type flip-flop (DFF), also known as data lacth, since a single data entry and external clock signal are used, as well as a positive edge is triggered.

Type D flip-flops, such as TTL 74LS74, can be made from flip-flops with SR or JK-based edge triggers (0 to 1 transition), depending on whether you want them to change their status on the positive or front edge (switching from 1 to 0) or on the negative or back edge of the clock pulse. Here we will assume a positive, pioneering trigger flip-flop.

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D-type Flip-flop and Accuracy Table

The operation of a type D flip-flop (DFF) is very simple, since there is only a single DATA entry called "D" and an additional hour of "CLK" input. This allows a single data bit (0 or 1) to be stored under the control of the clock signal, thereby making the D-type flip-flop a synchronous device, since the data in the inputs is transferred only to the flip-flop output on it.

Therefore, from the accuracy table, if the logic "1" (HIGH) exists in the DATA entry when a positive clock pulse is applied, the flip-flop SET and the "Q" are a logic "1". Likewise, if there is a logic "0" LOW in the DATA entry when another positive clock pulse is applied, the flip-flop resets and "0" in "Q" and "1" in Q are obtained.

The "Q" output of the D-type flip-flop then responds to the value of the "D" entry when the clock (CLK) input is HIGH. When the clock input is LOW, the condition in "Q", "1" or "0" is held until the clock signal goes to the next HIGH logic level "1". Therefore, the output in "Q" changes the status only when the clock entry changes from "0" (LOW) to "1" (HIGH), which makes it a D-type flip-flop with positive edge trigger. Note that flip-flops triggered by a negative edge work exactly the same way, except that the falling edge of the clock pulse is the triggering edge.

Now that we know how edge-triggering D-type flip-flops work, now let's look at connecting some to create a MOD counter.

Split-In-Two Counter

The edge-triggered D-type flip-flop is a convenient and versatile building block for creating a MOD counter or any other sequential logic circuit. By connecting the Q output to the input "D" again as shown and creating a feedback loop, we can convert it to a binary split counter using the clock input, since the Q output signal is always the opposite of the signal.

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Split-In-Two Counter and Schedule Diagram

Timing diagrams show that the output waveform "Q" has a frequency exactly half the frequency of the clock input, so the two-stop act as a frequency divider. If we add another D-type flip-flop, the output in "Q" becomes the input of the second DFF, then the output signal from this second DFF becomes a quarter of the clock input frequency, and so on. Therefore, for a number of flip-flops "n", the output frequency is divided by 2n in steps of 2.

Note that this frequency splitting method is very useful for use in sequential counting circuits. For example, a network frequency signal of 60 Hz can be reduced to a 1 Hz timing signal using a 60-by-60 split counter. A 6-by-6 split counter, 60Hz to 10Hz.

MOD-4 Counter

In addition to being technically a 1-bit storage device, a single flip-flop can be considered a MOD-2 counter in its own right, since it has a single output that results in two numbers, 0 or 1. But a single flip-flop produces a limited counting sequence on its own, so by connecting more flip-flops to form a chain, we can increase the counting capacity and create a MOD counter of any value.

If a single flip-flop can be considered a modulo-2 or MOD-2 counter, adding a second flip-flop gives us a MOD-4 counter that allows it to count in four separate steps. The overall effect will be to divide the original clock input signal into four. Then, the binary array for this 2-bit MOD-4 counter will be: 00, 01, 10 and 11.

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MOD-4 Counter and Timing Schema

For simplicity, note that the switching transitions of QA, QB, and CLK are shown simultaneously in the above schedule scheme, although this connection represents an asynchronous counter. In reality, there will be a very small switching delay between the implementation of the positive outgoing time (CLK) signal and outputs in QA and QB.

We can visually show the operation of this 2-bit asynchronous counter using a table of accuracy and a status diagram.

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MOD-4 Counter Status Schema

By reading qa and QB values from the accuracy table of the counter, we can see that the number is 00 when it is QA = 0 and QB = 0. After clock pulse application, the values are QA = 1, QB = 0, and the result is 01. After the next hour pulse arrives, the values change and qa = 0 becomes QB = 1, returns a number of 10. Finally, the values are QA = 1, QB = 1, giving an 11 count. The application of the next hour pulse causes the count to return to 00, and then counts continuously in a binary order: 00, 01, 10, 11, 00, 01 … like.

Then we found that a MOD-2 counter consists of a single flip-flop and requires two flip-flops that allow a MOD-4 counter to count in four separate steps. We can easily add another flip-flop to the end of a MOD-4 counter and create a MOD-8 counter that gives us a binary count sequence of 23 from 000 to 111 before going back to 000.

MOD-8 Counter and Status Diagram

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Therefore, before repeating itself, we can create mod counters so that the mod numbers have a natural number of 2n states, which give counters with 2, 4, 8, 16 and so on. However, sometimes it is necessary to have a module counter that resets its count during the normal counting process and does not have a module with the power of 2. For example, a counter whose module is 3, 5, 6, or 10.

MOD "m" Counters

Counters, synchronous or asynchronous progress are counted one by one in an adjusted binary progress, and as a result, an "n"-bit counter naturally functions as a modulo 2n counter. However, using one or more external logic gateways, we can create mod counters to count to any value we want using one or more external logic gateways, causing this to bypass several output state and end at any count, resetting the counter to zero.

In the case of modulo "m" counters, they do not count to all possible states, instead they count to "m", and then return to zero. Obviously, "m" is a number less than 2n, (m < 2n). So, how do we get the binary counter to return to zero during its count?

Fortunately, in addition to counting, counting up or down, it can also have additional entries called CLEAR and PRESET, which make it possible to clear counters to zero, (all Q = 0), or preset the counter to a starting value. The TTL 74LS74 has active-low Preset and Clear inputs.

For simplicity, suppose that all CLEAR entries are interconnected, and that there are active-high entries that allow flip-flops to run normally when the Clear entry is equal to 0 (LOW). However, if the Clear input is at the "1" (HIGH) logic level, the next positive edge of the clock signal will reset all flip-flops to Q = 0, regardless of the value of the next clock signal.

Also, because all Clear entries are connected, a single pulse can be used to clear the outputs (Q) of all flip-flops to zero before counting begins to ensure that the count really starts from scratch. In addition, some large bit counters have an additional ENABLE or INHIBIT input pin that allows the counter to stop counting at any point in the counting cycle and maintain its current state before it is allowed to continue counting. This means that the counter can be stopped and started at any time without resetting outputs to zero.

MOD-5 Counter

Let's say that we want to design a MOD-5 counter, how can we do this. First we know that it is "m = 5", so it should be greater than 2n 5. Since2 is greater than 1 =2, 2 2 = 4, 23 = 8 and 8 5, we need a counter with at least three flip-flops. (N = 3) gives us a natural binary number from 000 to 111 (0 to 7 de deities).

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MOD-8 Counter and Accuracy Table

Since we want to create a MOD-5 counter, we need to change the above 3-bit counter circuit to reset itself after counting to 5. This is a counting sequence: 1→2→3→. 4→5→fly, etc.

A MOD-5 counter will produce a 3-bit binary count sequence from 0 to 4, since 000 is a valid counting state and gives us the binary count order: 000, 001, 010, 011, 100. That's why we need a counter. It will produce an output condition such as QA = 1, QB = 0, and QC = 1 in pairs, as shown in the following status diagram.

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MOD-5 Counting Array

With the help of a 3-entry AND pass (TTL 74LS11) and an inverter or NOT gateway (TTL 74LS04), we can decode this output status of 101 (5) to give us a signal to reset the meter (Clr). ). The inputs of the combinational logic circuit consisting of an inverter and a digital logic AND gateway are connected to the 3-bit counter outputs of QA, QB and QC, respectively.

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The output of the 3-entry AND gateway will therefore be "0" (LOW) at the logic level for any input combination other than the input sequence we want.

In binary code, the number of output sequences will look like this: 000, 001, 010, 011, 100.

Although the counter appears to be counting to 101, when the asynchronous counting sequence reaches the next binary state of 101 (5), the combinational logic decoding circuit will detect this 101 condition, so that the AND gateway will produce a level of logic. 1 (HIGH) output returns the counter to its first zero state. Thus, the counter remains only a few nanoseconds in this 101 temporary state before resetting back to 000.

Therefore, we can use the input decoding of the AND gateway to reset the counter to zero after the output of the 5 (decimal) count that gives us the required MOD-5 counter. When output from the decoding circuit is LOW, it has no effect on the counting order.

MOD-5 Counter and Accuracy Table

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Next, around a basic counter to produce any type of MOD Counter that we need, we can use synchronous or asynchronous combinational logic decoding circuits, since unique output states can be decoded to reset the desired number of counters.

In our simple MOD-5 example above, we used a 3-input AND gateway to decode the 101 binary output state, but any logic circuit can be used to reset flip-flops as many as necessary.

However, one of the disadvantages of using an asynchronous counter to produce mod counters of any size in the desired number is that unwanted effects called "glitches" can occur when the counter reaches the reset state.

During this short period of time, the counter outputs may receive an incorrect value, so it is sometimes better to use synchronized counters as modulo-m counters, since all flip-flops are clocked by the same time signal, changing the state at the same time.

MOD-10 Counter

A good example of a modulo-m counter circuit that uses external combination circuits to produce a counter with 10 modules is the decimal counter. De tenth(10-divide) counters, such as the TTL 74LS90, have 10 conditions during counting, making the digital display suitable for the human interface where necessary.

The decimal number has four outputs that produce a 4-bit binary number, and using external AND and OR gates, we can detect the occurrence of the 9th counting state to reset the counter to zero. As with other mode counters, it takes a single input time pulse and counts repeatedly from 0 to 9.

When the number reaches 9 (binary 101), the counter returns to 0000 instead of continuing to 1010. The basic circuit of the ten-year counter can be made from JK flip-flops (TTL 74LS73), which change the situation negatively.

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MOD-10 Decimal Counter


About MOD Counters in this tutorial, we found that binary counters are sequential circuits that produce binary bit arrays as a result of a clock signal, and that the status of a binary counter is determined by the special combination that all counter outputs form together.

The number of different output states that a counter can generate is called the module or module of the counter. Module (or MOD number) of a counter is the total number of unique states that a mod-n counter passes through in an exact counting cycle, where it is also defined as a dividing counter to an n.

The module of a counter is given as follows:2 n where n = number of flip flops. Thus, 3 flip-flop counters will have a maximum 23 = 8 counting status and will be called mod-8 counters. The maximum binary number that can be counted by the counter is 2n–1, and the maximum count is (111)2 =2 3–1 =7 10. The counter then counts from 0 to 7.

Common MOD counters include those with MOD numbers 2, 4, 8, and 16, and can be configured to count any predetermined value except a maximum2 n module value with the use of external combination circuits. In general, any "m" number of flip-flop edits can be used to create any MOD counter.

A common module for counters with truss arrays is ten (1010), called MOD-10. A counter with ten states during it is known as a ten-counter counter. Ten-point counters are useful for interfaces to digital displays. Other MOD counters include the MOD-6 or MOD-12 counter, which have applications during digital hours to display the time of day.