In synchronous counters, all Flip-Flops in the circuit are triggered simultaneously. Instead of triggering the common clock pulse in order, as with the asynchronous counter, it triggers all Flip-Flops at the same time. If the flip-flop output changes to the next state, the values of the J and K inputs determine. In the case of J=K=0, Flip-Flop maintains its output state, while in J=K=1, it shows the "not" (inted= of the previous output state) on the output. The only input to the circuit is the clock pulse.
The synchronous counter can be designed in the desired Mode. The design process is as follows. The next situation should be taken into account when designing. The values that the J and K entries that will provide this status should receive are then transferred to the Karnaugh Map. Here, appropriate simplifications are made and the logistics required to control the inputs of Flip-Flops are found and the circuit is designed.
In the previous Asynchronous binary counter tutorial, we found that the output of a counter stage is directly connected to the clock input of the next counter stage, and so on throughout the chain.
The result of this is that the Asynchronous counter suffers from what is known as "Propagation Delay", in which the timing signal is delayed somewhat throughout each flip-flop.
However, with the Synchronous Counter, the external clock signal is connected to the clock input of each single flip-flop within the counter, so that all flip-flops are clocked simultaneously (in parallel) giving a fixed time. In other words, changes in output occur in "synchronization" with the clock signal.
The result of this synchronization is that all single output bits change state at exactly the same time in response to the common clock signal, without ripple effect and therefore propagation.
Note above that external clock pulses (pulses to be counted) are directly connected to each of the JK flip-flops in the opposite chain, and both J and K inputs are connected in transition mode, but only the first flip-flop is connected to HIGH, logical 1 in FFA (LSB). Flip-flop is allowed to switch every hour. The synchronous counter then follows a predetermined sequence of states in response to the common clock signal, advancing a state for each pulse.
The J and K inputs of the flip-flop FFB are directly connected to the QA output of the flip-flop FFA, but the J and K inputs of the flip-flop FFC and FFD are also driven through separate AND(AND() passes, which are also provided by signals from FFC and FFD. These additional VE gates produce the necessary logic for the JK inputs of the next stage.
If we allow each JK flip-flop to switch depending on whether all previous flip-flop outputs (Q) are "HIGH", we can achieve the same counting order as the asynchronous circuit, but without ripple, since each flip-flop will be clocked in this circuit at exactly the same time.
Then, since there is no natural propagation delay in synchronous counters, since all counter stages are triggered in parallel at the same time, the maximum operating frequency of such a frequency counter is much higher than a similar asynchronous counter circuit.
4-bit Synchronous Counter Waveform Schedule Scheme
Because this 4-bit synchronous counter counts sequencing every hour pulse, the outputs obtained count upwards from 0 (0000) to 15 (1111). Therefore, this type of counter is also known as the 4-bit SyncHronous Up Counter.
However, we can easily create a 4-bit Synchronous Down Counter by connecting the AND doors to the Q output of flip-flops, as shown to produce a waveform timing diagram inverse of the above. Where the counter starts with HIGH ( 1111 ) and counts backwards in applying the pulse to zero ( 0000 ) every hour before repeating it again.
Binary 4-bit SyncHronous Down Counter
Because synchronous counters are created by connecting flip-flops together, and any number of flip-flops can be connected together, or "cascading" to create a "n-split" binary counter, the "MOD" number is still valid as it is. For asynchronous counters, a decimal counter or BCD counter with numbers from 0 to 2n-1can be created with truncated arrays. All we need to increase the MOD number of a synchronous counter up or down is an additional flip-flop and the VE door opposite it.
Ten 4-bit SyncHronous Counter
It can also be created in a 4-bit tenner synchronizer using synchronous binary counters to produce a counting sequence from 0 to 9. After the requested state sequence reaches the number "1001", the counter returns to "0000".
Additional AND gates detect that the counting sequence has reached "1001" (Binary 10), causing the flip-flop FF3 to switch at the next hour pulse. Flip-flop FF0 switches every hour. Thus, the count is reset and the synchronous decimal number is reproduced at "0000".
We can easily rearrange the additional VE gates in the counter circuit above to produce other counting numbers, such as a Mod-12 counter that counts 12 statuses from "0000" to "1011" (0 to 11).
Triggering a Synchronized Counter
Synchronous Counters use flip-flops triggered from the edge that changes states on the "positive edge" (rising edge) or "negative edge" (falling edge) of the clock pulse at the control entry.
In general, synchronous counters are counted on the rising edge, where the clock signal switches from low to high, and asynchronous surge counters are counted on the falling edge, where the clock signal switches from high to low.
It may seem unusual for surge counters to use the falling edge of the clock loop to change the state, but this makes it easier to link counters together because the most important bit (MSB) of a counter can run the next time entry.
The next bit must change the state when the previous bit changes from high to low – at the point where a move for the next bit should occur. Synchronous numberers typically have an execution and a move input(pinine) to connect the numbers together without creating any propagation delays.
- Synchronous Numberers can be made from Toggle or D-type flip-flops.
- Synchronous counters are easier to design than asynchronous counters.
- Flip-flops are called synchronous counters because they are clock input.
- They're all clocked together at the same time as the same time signal.
- Because of this common clock pulse, all output states change at the same time.
- With all clock entries connected, there is no natural propagation delay.
- Synchronous counters are sometimes called parallel counters because the watch feeds parallel to all flip-flops.
- The internal memory circuit tracks the current state of the numberers.
- The counting sequence is controlled using logic gates.
- In general, faster operation can be achieved compared to asynchronous counters.